A printed circuit board, such as one used in a solid state drive (SSD), may have a memory controller and one or more memory devices attached to one or more surfaces of the printed circuit board. The memory controller and the one or more memory devices, among other components, are mounted on the printed circuit board. The memory controller is responsible for writing data to the memory devices and reading data stored on the memory devices. The memory controller and memory devices each contain a set of signal pins. These signal pins include data signal pins, address signal pins, or command signal pins, or a combination thereof. These signal pins are functionally organized as buses. Each type of signal pin can have its own bus, such as a data bus, or a single set of signal pins can carry multiple types of signals, forming a multiplex bus.
Traces are formed on the surfaces of, or within, the printed circuit board to carry electrical signals between the signal pins of the memory controller and the memory devices. A trace best carries signals when it is short and as direct as possible between an origin pin and a desired destination pin or pins. When a trace is laid out on or within the printed circuit board connecting a plurality of pins such that the trace has a long length, directional changes, or stubs, the signal quality may be degraded, which leads to a slower operation speed for the system.
As printed circuit boards increase in size and complexity, often with a plurality of components mounted on both sides of the printed circuit board, longer and more complex traces may be required to connect each signal pin of the memory controller to a plurality of signal pins on each memory device. Traces are laid out around the layout of the signal pins and around other traces, so they may need to take an indirect path and they may cross over each other in order to reach their desired destination, requiring additional layers to the printed circuit board.
FIG. 1 shows an example of a NAND flash memory device 100, according to the prior art. The NAND flash memory device 100 comprises a plurality of unique data signal pins. In FIG. 1, the NAND flash memory device 100 includes a top eight bit port 102 and a bottom eight bit port 104. The top eight bit port 102 includes an upper eight unique signal pins 106, numbered 0 through 7. The bottom eight bit port 104 includes a lower eight unique signal pins 108, also numbered 0 through 7. The signal pins 106 and 108 may form a multiplex bus that transmits data signals, address signals, or command signals at different times using a method of time-division multiplexing. Therefore, the signal pins 106 and 108 may carry data signals, address signals, or command signals at different times. The NAND flash memory device 100 also includes one or more additional signal pins 110 and 138 for control, power, or any other suitable function.
FIG. 2 shows an example of a configuration of two NAND flash memory devices 212 and 214 placed on opposite surfaces of a printed circuit board 211, according to the prior art. The printed circuit board 211 has a first major surface 213 and a second major surface 215 opposite the first major surface 213. A first NAND flash memory device 212 is attached to the first major surface 213 of the printed circuit board 211, and a second NAND flash memory device 214 is attached to the second major surface 215 of the printed circuit board 211. The first NAND flash memory device 212 and the second NAND flash memory device 214 may be the NAND flash memory device 100 shown and described in connection with FIG. 1, above. While the first NAND flash memory device 212 is shown in FIG. 2 to be slightly offset from the second NAND flash memory device 214 for clarity, the first NAND flash memory device 212 may overlap any portion of the second NAND flash memory device 214.
As previously described in connection with FIG. 1, the first NAND flash memory device 212 includes an upper eight unique signal pins 206 and a lower eight unique signal pins 208. The second NAND flash memory device 214 similarly includes an upper eight unique signal pins 207 and a lower eight unique signal pins 209. In total, the first and second NAND flash memory devices 212 and 214 include four sets of eight unique signal pins each, with each set of eight data signal pins numbered 0 through 7. Each of the eight unique signal pins of a set matches and is identically numbered to one of the eight unique signal pins of every other set.
Because the first NAND flash memory device 212 overlaps the second NAND flash memory device 214, one or more non-matching pairs of data signals pins of the first and second NAND flash memory devices 212 and 214 are located proximate to each other. For example, in FIG. 2 an upper data signal pin 206 of the first NAND flash memory device is numbered 3, and is located proximately above lower data signal pin 207 of the second NAND flash memory device numbered 4.
FIG. 3 shows an example of a conventional layout of traces 316, 318, and 320 for two NAND flash memory devices 312 and 314 placed on opposite sides of a printed circuit board 311, according to the prior art. Again, the first NAND flash memory device 312 and the second NAND flash memory device 314 may be the NAND flash memory device 100 shown and described in connection with FIG. 1, above. The first NAND flash memory device 312 and the second NAND flash memory device 314 may be positioned in a similar manner as the first NAND flash memory device 212 and the second NAND flash memory device 214 as shown and described in FIG. 2.
Three traces 320, 316, and 318 numbered DATA1, DATA3, and DATA6, respectively, are a part of a multiplex bus 305. While three traces 320, 316, and 318 are shown, multiplex bus 305 may include additional traces. As discussed above in connection with FIG. 1, the multiplex bus 305 transmits data signals, address signals, or command signals at different times using time-division multiplexing. To facilitate transmission of data, address, and command signals on the multiplex bus 305, each trace 316, 318, and 320 must be connected to specific signal pins of the first and second NAND flash memory devices 312 and 314: 1) one of the upper eight unique signal pins 306 of the first NAND flash memory device 312; 2) the matching one of the lower eight unique signal pins 308 of the first NAND flash memory device 312; 3) the matching one of the upper eight unique signal pins 307 of the second NAND flash memory device 314; and 4) the matching one of the lower eight unique signal pins 309 of the second NAND flash memory device 314. For example, the trace 316 numbered DATA3 must be connected to the signal pins 306, 307, 308, 309, all of which are numbered 3. Because the multiplex bus 305 transmits command signals at certain times, so the signal pins of the first and second NAND flash memory devices 312 and 314 must be connected by traces 316 in the manner described above. A signal pin 306 or 308 may not be connected arbitrarily to a non-matching signal pin 307 or 309 because, when the multiplex bus 305 is transmitting command signals, the signal pins may correspond to individual bits of an encoded binary command. For example, pin 0 may be the least significant bit and pin 7 the most significant bit of an 8 bit command (with intervening pins corresponding to intervening bits). For a command which is sent from a memory controller (shown in FIG. 4, below) to be correctly interpreted by the NAND flash memory devices 312 and 314, for example, this order must be strictly preserved. Thus, simply arbitrarily connecting non-matching signal pins of the multiplex bus 305 will cause errors or may cause the first and second NAND flash memory devices 312 and 314 to not function entirely.
Because the traces 316, 318, and 320 must be routed in this manner, there is routing congestion of the traces 316, 318, and 320 on and within the printed circuit board 311. For example, routing the trace 316 to connect to the four signal pins 306, 307, 308, and 309 that are all numbered 3, which are located disparately on the first and second NAND flash memory devices 312 and 314, results in a number of congestion problems for the trace 316. The trace 316 is long and includes four stubs 317a-d. Each stub 317a-d is a short trace segment that is connected to the trace 316 at one end only. The trace 316 must cross over other traces 318 and 320 at one or more points proximate to the first and second NAND flash memory devices 312 and 314, requiring routing through additional layers of the printed circuit board 311 to prevent the overlapping traces 316, 318, and 320 from coming into contact with each other. The congestion of the traces 316, 318, and 320 also causes degradation of signal quality for the signals carried by the traces 316, 318, and 320 which leads to a slower operation speed of the multiplex bus 305.
FIG. 4 shows an example of a conventional layout of traces connecting a NAND memory controller 401 to two NAND flash memory devices 412 and 414 placed on opposite sides of a printed circuit board 411, according to the prior art. Again, the first NAND flash memory device 412 and the second NAND flash memory device 414 may be positioned and configured in a similar manner as the first NAND flash memory device 212 and the second NAND flash memory device 214 as shown and described in FIG. 2. The layout of the traces 416, 418, and 420 between the first and second NAND flash memory devices 412 and 414 is similar to the layout of the traces 316, 318, and 320 as shown and described in FIG. 3.
The NAND memory controller 401 includes unique signal pins 419, numbered 0 through 7. Each signal pin 419 of the NAND memory controller 401 matches four specific signal pins of the first and second NAND flash memory devices 412 and 414: 1) the matching one of the upper eight unique signal pins 406 of the first NAND flash memory device 412; 2) the matching one of the lower eight unique signal pins 408 of the first NAND flash memory device 412; 3) the matching one of the upper eight unique signal pins 407 of the second NAND flash memory device 414; and 4) the matching one of the lower eight unique signal pins 409 of the second NAND flash memory device 414.
As previously discussed in connection with FIG. 3, each trace 416, 418, and 420 must connect to matching unique signal pins 406, 407, 408, and 409, such those signal pins numbered 3 connected to the trace 416. In addition to connecting the matching unique signal pins 406, 407, 408, and 409 of the first and second NAND flash memory devices 412 and 414, each trace 416, 418, and 420 must also be connected to a matching unique signal pin 419 of the NAND memory controller 401. For example, the trace 416 numbered DATA3 is connected a signal pin 419 labeled 3 of the NAND memory controller 401, and to the four data signal pins 406, 407, 408, and 409 numbered 3 of the first and second NAND flash memory devices 412 and 414. Again, this is because the signal pins 406, 407, 408, and 409 also may not be simply arbitrarily connected to a non-matching signal pin 419 of the NAND memory controller 401 because, when the multiplex bus 305 is transmitting command signals between the NAND memory controller 401 and the first and second NAND flash memory devices 412 and 414, the command signals must be transmitted in a fixed order.
Thus, in addition to the congestion of the traces 416, 418, and 420 between the first and second NAND memory devices 412 and 414 previously described in FIG. 3, the connection to the matching unique signal pins 419 of the memory controller 401 may require the traces 416, 418, and 420 to further cross over each other at one or more points proximate to the NAND memory controller 401, creating further congestion of the traces 416, 418, and 420 on or within the printed circuit board 411.
The present invention provides a novel approach for alleviating printed circuit board routing congestion without compromising the integrity of buses connecting components on the printed circuit board.